1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of manufacturing semiconductor devices with different insulation thicknesses on the same semiconductor substrate and the resulting integrated circuit products.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
For many early device technology generations, the gate electrode structures of most transistor elements have comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the so-called short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, some gate electrode structures are comprised of a so-called high-k dielectric layer (k value greater than 10) and one or more metals layers that act as the gate electrode or as a work-function adjusting material, i.e., a high-k/metal gate (HK/MG) configuration. Such high-k/metal gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1D depict one illustrative prior art method for forming an HK/MG replacement gate structure using a gate last technique. As shown in FIG. 1A, the process includes the formation of a basic transistor structure 13 above a semiconducting substrate 10 in an active area defined by a shallow trench isolation structure 11. At the point of fabrication depicted in FIG. 1A, the device 13 includes a dummy or sacrificial gate insulation layer 12, a dummy or sacrificial gate electrode 14, sidewall spacers 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 10. The various components and structures of the device 13 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 12 may be comprised of silicon dioxide, the sacrificial gate electrode 14 may be comprised of polysilicon, the sidewall spacers 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NFET devices and P-type dopants for PFET devices) that are implanted into the substrate 10 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 13 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high-performance PFET transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 13 have been formed and a chemical mechanical polishing process (CMP) has been performed to remove any materials above the sacrificial gate electrode 14 (such as a protective cap layer (not shown) comprised of silicon nitride) so that the sacrificial gate electrode 14 may be removed.
As shown in FIG. 1B, one or more etching processes are performed to remove the sacrificial gate electrode 14 and the sacrificial gate insulation layer 12 to thereby define a gate opening or cavity 20 where a replacement gate structure will subsequently be formed.
Typically, the sacrificial gate insulation layer 12 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 12 may not be removed in all applications. Even in the case where the sacrificial gate insulation layer 12 is removed, a very thin interfacial layer of silicon dioxide (not shown) will typically form on the substrate 10 within the gate cavity 20.
Next, as shown in FIG. 1C, various layers of material that will constitute part of the replacement gate structure 30 are formed in the gate cavity 20. In one illustrative example, the replacement gate structure 30 is comprised of a high-k gate insulation layer 30A having a thickness of approximately 2 nm, a work function adjusting layer 30B comprised of a metal (e.g., a layer of titanium nitride with a thickness of 2-5 nm) and a bulk metal layer 30C (e.g., aluminum, tungsten, etc.). Ultimately, as shown in FIG. 1D, one or more chemical mechanical polishing (CMP) processes are performed to remove excess portions of the gate insulation layer 30A, the work function adjusting layer 30B and the bulk metal layer 30C positioned outside of the gate cavity 20 to define the replacement gate structure 30.
In some situations, integrated circuit products are formed with semiconductor devices, such as transistors, that have different gate insulation thicknesses. For example, input/output circuits may be formed using transistors having thicker gate insulation layers, as compared to logic circuits or SRAM cells that are formed using transistor devices having relatively thinner gate insulation layers. In general, all other things being equal, the thinner the gate insulation layer of a transistor device, the faster will be its switching speed. Thus, transistor devices with very thin gate insulation layers are used in the circuits that demand higher performance, e.g., faster switching speeds. However, such increased performance in a transistor is not without “costs,” as, all other things being equal, transistor devices with relatively thinner gate insulation layers tend to exhibit greater “leakage,” i.e., off-state leakage currents, as compared to transistor devices with relatively thicker gate insulation layers. As a net result, circuits made with transistor devices having relatively thinner gate insulation layers tend to consume more power than circuits made with corresponding transistors having thicker gate insulation layers. Excess power consumption is particularly problematic for integrated circuit products that are intended for use in mobile applications, such as, for example, cell phones and laptops, as reducing the power consumed by the integrated circuit product during operation is very important due to the limited battery life of the device. Thus, in some cases, integrated circuit products may use high-speed (thin gate insulation) transistor devices only where the higher performance they provide is absolutely needed, and use transistor devices (with relatively thicker gate insulation layers) on some or all of the other circuits in the device to reduce the overall power consumed by the consumer product during operation. Another situation where an integrated circuit product may be formed with devices having different gate insulation thicknesses is where the various circuits on the integrated circuit product, i.e., the chip, operate at different voltage levels, which is a relatively common situation in many modern integrated circuit products. Typically, all other things being equal, the transistor devices that will be subjected to a higher operating voltage will have a thicker gate insulation layer as compared to transistor device that will be subjected to a lower operating voltage.
FIGS. 2A-2E depict one illustrative prior art method of forming an integrated circuit product 33 comprised of transistor devices 32, 34 having different gate insulation thicknesses using a replacement gate process. As shown in FIG. 2A, a first transistor 32 that is intended to have a relatively thicker final gate insulation layer will be formed in and above an active region 10A that is defined in the substrate 10 via the illustrative isolation regions 11. Also depicted in FIG. 2A is a second transistor 34 that is intended to have a relatively thinner final gate insulation layer than that of the first transistor 32. The second transistor 34 will be formed in and above an active region 10B that is defined in the substrate 10 via the illustrative isolation regions 11. At the point of fabrication depicted in FIG. 2A, the various structures of the device 33 have been formed and a chemical mechanical polishing process (CMP) has been performed to remove any materials above the sacrificial gate electrode 14 (such as a protective cap layer (not shown) comprised of silicon nitride) so that the sacrificial gate electrode 14 may be removed.
As shown in FIG. 2B, one or more etching processes have been performed to remove the sacrificial gate electrode 14 of both of the devices 32, 34. After the sacrificial gate electrode 14 is removed, the sacrificial gate insulation layer 12 remains in place in both of the devices 32, 34. However, as described more fully below, the gate insulation layer 12 will be part of the overall final gate insulation for the device 32, i.e., the gate insulation layer 12 is not sacrificial in nature as it relates to the device 32 that will ultimately have a relatively thicker overall stack of gate insulation material as compared to the device 34. Thus, the thickness of the gate insulation layer 12 is typically selected to be the desired thickness of the silicon dioxide portion of the final stack of gate insulation material that will be formed for the device 32, with the allowance for additional high-k insulating material that will be formed above the layer 12 for the device 32, as described more fully below. The final stack of gate insulation material for the device 32 will include the layer of gate insulation material 12 and the to-be-formed layer of high-k insulating material. For example, in one embodiment, the layer of insulation material 12 may be a layer of silicon dioxide having a thickness of about 3-5 nm.
FIG. 2C depicts the device after several process operations have been performed. First, a patterned etch mask 36, e.g., a patterned photoresist mask, was formed above the substrate 10 using known photolithography tools and equipment. The patterned etch mask 36 covers the device 32 but exposes the device 34 for further processing. Next, an etching process was performed through the patterned etch mask 36 to remove the sacrificial gate insulation layer 12 on the exposed device 34 so as to thereby define a gate cavity 34C where a replacement gate structure will subsequently be formed for the device 34. As noted above, when the sacrificial gate insulation layer 12 is removed, a very thin interfacial layer of silicon dioxide (not shown) will typically form on the substrate 10 within the gate cavity 34C.
FIG. 2D depicts the device after several process operations have been performed. First, the patterned etch mask 36 was removed. This results in a gate cavity 32C for the device 32, i.e., the space between the spacers 16 and above the remaining original gate insulation layer 12. Thereafter the various layers of material that will be part of the final replacements gate structures 32G, 34G are formed in the gate cavities 32C, 34C. In one illustrative example, this involves formation of the above-described high-k gate insulation layer 30A, work function adjusting layer 30B and bulk metal layer 30C (e.g., aluminum, tungsten, etc.). Ultimately, as shown in FIG. 2E, one or more chemical mechanical polishing (CMP) processes are performed to remove excess portions of the gate insulation layer 30A, the work function adjusting layer 30B and the bulk metal layer 30C positioned outside of the gate cavities 32C, 34C to define the replacement gate structures 32G, 34G, respectively. As depicted, the device 32 has a greater thickness 32T of gate insulation materials (the gate insulation layer 12 plus the high-k gate insulation layer 30A) as compared to the thickness 34T of the device 34, which only has the high-k gate insulation layer 30A. To the extent that an interfacial layer is present on the device 34, it would be considered to be part of this overall thickness of gate insulation material. However, even if such an interfacial layer were present, it is so thin that, even when considered to be combined with the high-k gate insulation layer 30A, the device 34 would still have a lesser thickness of gate insulation material as compared to the device 32.
The present disclosure is directed to various methods of manufacturing semiconductor devices with different insulation thicknesses on the same semiconductor substrate and the resulting integrated circuit products.